`ifndef _ral_sys_REG_PRJ_rtl_
`define _ral_sys_REG_PRJ_rtl_

`include "vmm_ral_host_itf.sv"

module ral_sys_REG_PRJ_rtl(vmm_ral_host_itf.slave hst,
                           vmm_ral_host_itf.master sys_cfg,
                           vmm_ral_host_itf.master sys_status,
                           vmm_ral_host_itf.master sys_irq);
always @(*)
   begin
      hst.ack = 0;
      sys_cfg.sel[3:0] = 'b0;
      if (hst.adr >= 'h0 && hst.adr < 'h101) begin
         sys_cfg.sel[3:0] = hst.sel[3:0];
      end
      sys_status.sel[3:0] = 'b0;
      if (hst.adr >= 'h200 && hst.adr < 'h20d) begin
         sys_status.sel[3:0] = hst.sel[3:0];
      end
      sys_irq.sel[3:0] = 'b0;
      if (hst.adr >= 'h600 && hst.adr < 'h60d) begin
         sys_irq.sel[3:0] = hst.sel[3:0];
      end

   end




assign sys_cfg.adr = hst.adr - 'h0;
assign sys_cfg.wdat[31:0] = hst.wdat[31:0];
assign sys_cfg.wen = hst.wen;

assign sys_status.adr = hst.adr - 'h200;
assign sys_status.wdat[31:0] = hst.wdat[31:0];
assign sys_status.wen = hst.wen;

assign sys_irq.adr = hst.adr - 'h600;
assign sys_irq.wdat[31:0] = hst.wdat[31:0];
assign sys_irq.wen = hst.wen;


reg [31:0] _hst_rdat;
always @(*)
   begin: hst_muxout
      unique casez ({|sys_cfg.sel[3:0],
		               |sys_status.sel[3:0],
		               |sys_irq.sel[3:0]})
         3'b1??: begin
            _hst_rdat = sys_cfg.rdat[31:0];
            hst.ack = sys_cfg.ack;
         end
         3'b?1?: begin
            _hst_rdat = sys_status.rdat[31:0];
            hst.ack = sys_status.ack;
         end
         3'b??1: begin
            _hst_rdat = sys_irq.rdat[31:0];
            hst.ack = sys_irq.ack;
         end
         default: begin
            _hst_rdat = 0;
            hst.ack = 0;
         end
      endcase
   end
assign hst.rdat[31:0] = _hst_rdat;


endmodule
`endif

